1. Field of the Invention
The present invention generally relates to a device for controlling a setup/hold time of an input signal, and more specifically, to a technique to control the setup/hold time of various control signals applied from an input buffer without physically changing the control device.
2. Description of the Prior Art
FIG. 1 is a circuit diagram illustrating a conventional device for controlling setup/hold time of input signal.
The conventional device for controlling a setup/hold time of an input signal comprises inverters IV1˜IV4 for performing a driver function, MOS capacitors C1˜C4 for performing a signal delay function, metal option unit 2 and 3, and a latch 4.
Here, the inverters IV1 and IV2 output signals by driving an address, a command signal or input data applied from an input buffer 1. The inverter IV3 outputs a signal by driving an output signal of the metal option unit 2. The inverter IV4 drives an output signal of the metal option unit 3 to provide a global bus line control signal GB_BL to the latch 4.
The metal option units 2 and 3 comprising metal option switches MO1˜MO4 selectively control the MOS capacitors C1˜C4 to control setup/hold time of the global bus line control signal GB_BL.
The MOS capacitors C1 and C2 are selectively connected to an output terminal of the inverter IV2 by the metal option switches MO1 and MO2. The MOS capacitors C3 and C4 are selectively connected to an output terminal of the inverter IV3 by the metal option switches MO3 and MO4.
The latch 4 latches the global bus line control signal GB_BL in synchronous to a clock signal CLK to output the latched signal into a global bus line (not shown). Here, in order that the global bus line control signal GB_BL inputted into the latch 4 may be valid, the global bus line control signal GB_BL should be transmitted into the latch earlier than the clock signal CLK by a predetermined time (setup time). When the latch 4 performs a latch operation in synchronous to the clock signal, a state of the global bus line control signal GB_BL should be maintained for a predetermined time (hold time).
Here, the ideal condition is that the clock signal CLK is enabled after the setup time of the global bus line control signal GB_BL has passed, and the state of the global bus line control signal GB_BL for the hold time has been maintained.
However, it is difficult to satisfy the above ideal condition because signals inputted from outside of an actual chip through the input buffer 1 are influenced by length of an internal transmission line, various noises, capacitance or resistance, and so forth.
Accordingly, the device for controlling a setup/hold time of an input signal is designed to control the setup/hold time of the global bus line control signal GB_BL by selectively connecting signal delay devices such as the MOS capacitors C1˜C4.
In other words, the metal option switches MO1˜MO4 requiring physical apparatus are used to regulate the setup/hold time of the global bus line control signal GB_BL. As a result, since circuits of metal layers need to be physically changed to regulate the setup/hold time, the conventional device has a problem consuming a long time and a high cost.